⬥ Extensive Experience: Highly skilled VLSI/ASIC Design Engineer with a strong
background from front-end logic/architect to back-end implementation with chip
design companies, including roles at Google, Meta, Intel, Broadcom, and
Micron Technology.
⬥ Technical Expertise: Proficient in logic design/synthesis, timing closure, low
power design/verification, physical design, and various design verifications.
Extensive experience with industry-standard ASIC design/verification EDA-
toolset flows from RTL to GDSII.
⬥ Specialized Skills: Solid understanding of microprocessor architecture, bus
protocols, and networking/communication protocols. Skilled in power analysis,
optimization, and debugging using Synopsys and Cadence toolsets.
⬥ Collaborative Professional: Dedicated, hardworking, and independent, with a
strong ability to work and communicate effectively across organizations. Enjoys
teamwork and is capable of leading improvements in EDA flows with scripting
languages like TCL and Python.
⬥ Diverse Roles:Experience includes microprocessor development, ASIC/SoC
power engineering, IP logic design, and CAD/methodology engineering.
Notable projects involve high-performance microprocessors, power
prediction/reduction, timing analysis, and design flow development.
⬥ Tool Proficiency: Familiar with a wide range of EDA tools and software,
including Verilog, System Verilog, VHDL, Matlab, Synopsys Design/IC
Compiler, Cadence Innovus, and scripting languages such as Perl, Python,
and TCL.
EDUCATION:
⬥ M.S. in Electrical Engineering (MSEE): Northwestern Polytechnic University, Fremont, California
⬥ B.S. in Electrical Engineering (BSEE): University of Illinois, Urbana-Champaign, Illinois